Device: K5A3280YBC-T [TBGA69]
Manufacturer: Samsung
Part number description for this device:
Move the cursor over the box to highlight particular section| K5 | Samsung MCP Memory | |
| X | Device Type | A = NOR DB Flash + fCMOS SRAM B = NOR BB Flash + fCMOS SRAM C = Mitsubishi NOR + fCMOS SRAM D = NAND Flash + SDRAM E = NAND Flash + DDR SDRAM F = NOR DB Flash + NAND Flash G = Muxed NOR Flash + SDRAM H = NOR DB Flash + SDRAM J = NOR DB Flash + SDRAM K = De-Muxed NOR Flash + SDRAM L = De-Muxed NOR Flash + UtRAM M = NOR BB Flash + TFT SRAM N = Muxed NOR Flash + Muxed UtRAM P = NAND Flash + Muxed UtRAM Q = NAND Flash + UtRAM R = OneNAND + SDRAM S = UtRAM + fCMOS SRAM T = Mitsubishi NOR Flash + UtRAM U = Muxed NOR Flash + OneNAND V = NOR DB Flash + OneNAND W = OneNAND + DDR SDRAM X = Muxed NOR + SDRAM Z = NOR DB Flash + DDR SDRAM |
| XX | First Chip Density | - when 1st chip is NOR DB Flash (x8/x16) 32 = 32Mbit (8Mbit + 24Mbit) 33 = 32Mbit (16Mbit + 16Mbit) 63 = 64Mbit (16Mbit + 48Mbit) - when 1st chip is NOR BB Flash (x16) 16 = 16Mbit 32 = 32Mbit 64 = 64Mbit - when 1st chip is NAND Flash (x8) 12 = 512Mbit 28 = 128Mbit 56 = 256Mbit 57 = 256Mbit (x16) - when 1st chip is UtRAM 64 = 64Mbit 1G = 1Gbit 32 = 32Mbit - when 1st chip is Mitsubishi NOR Flash 64 = 64Mbit (4Mbit+4Mbit+28Mbit+28Mbit) - when 1st chip is Muxed NOR Flash 28 = 128Mbit (8Mx16, 16Bank) 56 = 256Mbit (16Mx16, 16Bank) 64 = 64Mbit (4Mx16, 16Bank) - when 1st chip is De-Muxed NOR Flash 28 = 128Mbit (8Mbit, 16Bank) 56 = 256Mbit (x16) 64 = 64Mbit (16Mbit+48Mbit) 66 = 64Mbit (4Mx16, 8Bank) - when 1st chip is OneNAND 12 = 512Mbit (x16) 56 = 256Mbit (x16) 1G = 1Gbit (x16) |
| XX | Second Chip Density | - when 2nd chip is fCMOS SRAM 17 = 16Mbit (x16) 40 = 4Mbit (x8 / x16) 41 = 4Mbit (x16) 80 = 8Mbit (x8 / x16) 81 = 8Mbit (x16) - when 2nd chip is TFT SRAM 21 = 2Mbit (x8) - when 2nd chip is NAND Flash 64 = 64Mbit (x8) - when 2nd chip is UtRAM 16 = 16Mbit (x16) 28 = 128Mbit (x16, Burst) 32 = 32Mbit (x16) 31 = 32Mbit (x16, Page) 64 = 64Mbit (x16, Burst) 66 = 64Mbit (x16) - when 2nd chip SDRAM 12 = 512Mbit (x16) 13 = 512Mbit (x32) 28 = 128Mbit (x32) 29 = 128Mbit (x16) 57 = 256Mbit (x16) 58 = 256Mbit (x32) - when 2nd chip is DDR SDRAM 12 = 512Mbit (x16) 13 = 512Mbit (x32) 28 = 128Mbit (x32) 29 = 128Mbit (x16) 57 = 256Mbit (x16) 58 = 256Mbit (x32) - when 2nd chip is Muxed SRAM 17 = 16Mbit (x16) 41 = 4Mbit (x16) 81 = 8Mbit (x16) - when 2nd chip is Muxed UtRAM 16 = 16Mbit (x16) - when 2nd chip is OneNAND 28 = 128Mbit (x16) 56 = 256Mbit (x16) |
| X | Operating Voltage Range | 8 = 1.7V to 1.9V A = 1.8V / 1.8V B = 2.6V / 2.6V C = 3.0V / 3.0V D = 2.6V / 1.8V E = 3.3V / 2.5V F = 2.8V H = 3.0V / 2.5V K = 1.9V / 1.9V L = 3.3V / 1.8V V = 3.3V / 3.3V Y = 2.7V to 3.3V - only 1st chip is NAND Flash 6 = 2.4V to 2.8V - when 1st chip and 2nd chip is different G = 1.8V / 1.8V, 3.0V / 1.8V J = 1.8V / 1.8V, 2.6V / 1.8V |
| X | Flash Boot Block Mode | A = Top & bottom boot block B = Bottom boot block C = Uniform block T = Top boot block 0None |
| X | Generation | M = 1st generation A = 2nd generation B = 3rd generation C = 4th generation D = 5th generation E = 6th generation F = 7th generation G = 8th generation |
| X | Package Type | A = FBGA (HF, LF) D = FBGA (LF) E = LGA (No BAll) F = FBGA H = LGA (LF) K = TBGA (Intell Ball Out) P = FBGA (OSP) S = FBGA (OSP LF) T = TBGA L = TBGA (LF) |
| X | 1st Chip Speed | - when 1st chip is NOR DB/BB & Mitsubishi NOR & UtRAM 2 = 65ns 3 = 85ns 7 = 70ns (except UtRAM) 8 = 80ns 9 = 90ns - when 1st chip is burst A = 100ns (C/F 40MHz) B = 100ns (C/F 54MHz) C = 90ns (C/F 40MHz) G = 90ns (C/F 54MHz) E = 88.5ns (C/F 54MHz) F = 70ns (C/F 66MHz) H = 14.5ns (C/F 54MHz) - when 1st chip is OneNAND J = 18.5ns (C/F 54MHz) K = 15ns (C/F 66MHz) - MCP common 0None N = No Bin (TPB) |
| XX | 2nd Chip Speed | - when 2nd chip is fCOM SRAM & UtRAM(Muxed) 10 = 100ns 18 = 18.5ns 50 = 50ns 55 = 55ns 60 = 60ns 70 = 70ns 85 = 85ns 90 = 90ns DS = Daisychain - when 2nd chip is Muxed SRAM 10 = 100ns 70 = 70ns 85 = 85ns 90 = 90ns DS = Daisychain - when 2nd chip is SDRAM/DDR SDRAM 15 = 15ns@CL2 60 = 6ns@CL3 75 = 7.5ns@CL3 85 = 8.5ns@CL3 90 = 9ns@CL3 95 = 9.5ns@CL3 1H = 10ns@CL2 1L = 10ns@CL3 9H = 9ns@CL2 DS = Daisychain - when 2nd chip is Burst UtRAM 54 = 54MHz 66 = 66MHz - when 2nd chip is OneNAND 76 = 76ns DS = Daisychain - MCP common 00 = None |
| X | Packing Type | T = Tape&Reel Number = Other(Tray, Tube, Jar) S = Stack |
| XX | Customer "Customer List Reference" |
Note: Part number description table describes usual part-numbering system for more chips, therefore this table can contain information, that might not be valid for the actually selected chip. The information here are provided on the best-effort basis and might be either inaccurate or incoplete. Therefore always check the latest datasheet of the chip for part number description detail. If you find some inaccuracy, let us please know.
go back to result pageSupported by programmers and programming adapters/modules:
| BeeHive204 | adapter/module: BGA-0246/0265 (70-0246/0265) = BGA-Bottom-2 (70-0246) + BGA-Top-11 ZIF-CS (70-0265) |
| BeeHive208S | adapter/module: BGA-0246/0265 (70-0246/0265) = BGA-Bottom-2 (70-0246) + BGA-Top-11 ZIF-CS (70-0265) |
| BeeProg2 | adapter/module: BGA-0246/0265 (70-0246/0265) = BGA-Bottom-2 (70-0246) + BGA-Top-11 ZIF-CS (70-0265) |
| BeeProg2C | adapter/module: BGA-0246/0265 (70-0246/0265) = BGA-Bottom-2 (70-0246) + BGA-Top-11 ZIF-CS (70-0265) |
